This invention relates generally to methods for manufacturing a conductor and more particularly to methods for manufacturing a conductor for use with semiconductor devices.
As is known in the art, a conductor is often formed on a substrate to provide, for example, a gate electrode for a field effect transistor (FET). The width of the gate electrode partially determines the gate length, and hence the charge transport characteristics, of the FET. In operation, when an FET turns on, a charge packet builds up under the gate electrode. In order to turn the FET off, the charge packet must be removed from under the gate electrode. By passing across a wide gate electrode the transit time of the charge packet, which is proportional to the width of such electrode, will be relatively long. Thus, by reducing the width of the gate electrode, the transit time of the charge packet across the gate electrode will decrease. This decrease in the transit time of the charge permits shorter time durations to remove the charge packet and hence permits an increase in the maximum operating frequency for the FET device. As is known in the art, a method to reduce the width of the gate electrode to submicron widths is the so-called electron beam lithography technique. This technique uses a beam of electrons, for example, to transfer a preprogrammed pattern directly to the wafer surface (direct write technique) or to form a master mask blank. With the direct write method, for each submicron step, each wafer must be individually placed in the electron beam apparatus; a very time consuming and expensive process, particularly for a production orientated line. Thus, while gate electrode width reduction is achieved using this technique, the expense of such equipment and lack of an acceptable production technique makes the direct write electron beam lithography technique impractical for certain applications. Mask generation using electron beam lithography is likewise high in cost.
A second technique involves the use of X-ray exposure systems. Currently collimated high intensity exposure sources are being developed. Currently this technique due to the lack of acceptable collimated sources, is not easily adaptable for production applications. For those applications, where the use of the above submicron lithography techniques are not cost effective, other methods of forming submicron conductors have been devised. A prior art method of forming a submicron conductor using micron photolithography includes the steps of: photolithographically forming an aperture in a masking layer to expose a portion of the substrate; over-plating a surface of such masking layer while protecting the exposed portion of the substrate to provide such aperture with a reduced, sized opening; and depositing a layer of metal through such reduced sized opening on to the exposed portion of the substrate, with the over-plating acting as a mask to restrict the width of such deposited metal substantially to the width of the sized opening. This method has several disadvantages including difficulty in controlling the plating process to provide an accurately sized opening to form accurately sized conductors, and further, the uniformity of resolution obtained by such a technique is often unacceptable in some applications.